Industries / RF & mmWave
Packaging that keeps the
loss budget intact.
High-frequency and mmWave modules live or die on the interconnect. We assemble GaN, GaAs, and antenna-in-package builds on low-loss substrates – fluxless, traceable, qualified, on US soil – for defense, radar, 5G, and satcom programs.
/ GaN & GaAs / AlN substrates / fluxless assembly / US-soil
Proof, from real RF builds
AlN, Rogers PTFE, low-loss substrate-matched attach
Ground-plane continuity, fluxless process
Sub-millimeter pitch capable
Full design rules, loss budgets, and build data available under NDA.
What we build for RF & mmWave
From eval board
to hermetic module.
RF eval boards, test vehicles, and production-intent modules – assembled around the signal path, not bolted on after it. The assembly choices that move your insertion loss happen here.
Every assembly choice that moves your insertion loss - flux-free reflow, die attach, and thin-film metallization - happens here, on US soil, for RF and mmWave programs.
- 01GaN and GaAs die attach for power amplifiers, LNAs, and switches
- 02Antenna-in-package (AiP) and module integration for mmWave front ends
- 03Flip-chip and wire-bond interconnect tuned for low parasitics
- 04Fluxless, maskless assembly on AlN for clean, low-loss interfaces
- 05Hermetic packages for moisture-sensitive, reliability-critical RF
- 063D heterogeneous integration to shorten interconnect and stack function
Wafer 2″–12″ · die→substrate, die→wafer, die→PCB · advanced packaging across the stack.
Why it matters
At mmWave, the package
is part of the circuit.
Signal integrity
Flux residue is dielectric loss sitting on your trace. Fluxless, maskless assembly keeps the interface clean, so the loss you measure is the loss you designed – not contamination you have to chase.
Thermal management
GaN power amplifiers dump heat into the substrate. AlN moves it out fast and stays dimensionally stable, holding junction temperature down so RF performance and reliability hold together over life.
Yield you can trace
Every build is inspected and recorded – X-ray, 3D AOI, and sub-micron metrology. Yield is a number we can show you, with the data behind it, not a claim.
Get these three right and a tight loss budget closes on the first build instead of the third – that is the schedule and cost difference for an RF program.
The substrate is
a design choice.
AlN for thermal and low loss. Sapphire and quartz where the dielectric matters. Si for CMOS-compatible integration. We match the carrier to the band, the power, and the reliability target.
Thin-film metallization, controlled underfills, and qualified attach materials round out the stack. Material selection and the rules that go with it are part of the materials conversation – full detail under NDA.
GaN-on-SiC
SiC is why it runs cool.
The attach is why it stays that way.
This one is the die's own growth substrate, not the carrier beneath it. GaN grown on SiC carries roughly 3.3 W/(cm·K) at room temperature — the reason a SiC-based amplifier runs cooler than the same design on silicon or sapphire, where published channel temperatures reach 320 to 370 °C at only about 6 W dissipated.
That substrate choice is made before the die reaches us. Everything below it is ours: the attach, the carrier, and the thermal path they form together.
ATTACH ROUTES — CHOSEN BY THERMAL BUDGET
AuSn eutectic
80Au/20Sn, fluxless. Re-melts at 280 °C, so it survives a later lid step and board-level SAC305 at 217 °C without floating the die. The route for hermetic, step-soldered builds.
Sintered silver
Processes at 200–250 °C under pressure, then stays solid to silver's 961 °C melting point. About 220 W/m·K by laser-flash. The route when power density or die area makes voiding the limiting risk. Not reworkable.
We run both. Which one a build gets is a calculation, not a house preference.
The GaN failure mode most spec sheets skip.
A GaN die with thick backside gold dissolves into the AuSn during reflow. The joint walks off eutectic, melts unevenly, and voids — and the process window looks fine right up until the X-ray.
The fix is an off-eutectic preform — 79/21, 78/22, or 75/25 — sized so the gold the die gives up carries the joint back to eutectic as it melts. Preform footprint runs 90 to 100% of the die. Flatness and a scrub during reflow do the rest.
The carrier is a CTE decision, and it is not close.
A GaN-on-SiC die expands with its substrate, about 3.7 ppm/°C. Put a 5 mm die on a 25 µm AuSn bondline and cycle it from the 280 °C solidus down to −55 °C, and the die-attach shear strain lands here:
- 2.3%Aluminum nitride, 4.4 ppm/°C — survivable
- 14%96% alumina, 7.9 ppm/°C — marginal
- 45%Bare copper, 17 ppm/°C — cracks die
That is the whole argument for an AlN carrier under a hard-soldered GaN die. When a joint still fails, the levers are a softer attach, a thicker bondline, a smaller die, or a better-matched carrier.
Qualified, not asserted: C-SAM and X-ray for voids and delamination, die shear to MIL-STD-883 Method 2019, wire-bond pull and ball shear to Methods 2011 and 2023, thermal cycling to Method 1010 from −55 to +125 °C with a second C-SAM after cycling. You get the failure-mode distribution, not just a pass count.
How we engage
Coupon first. Then scale.
We start with a test vehicle or coupon that exercises the hard part of your build – the attach, the interconnect, the thermal path – and prove it against real metrology before anyone commits a full lot.
One engineering team carries the program from that first coupon through qualification and production-intent. Reliability and test – thermal cycling, screening, hermetic test, MIL-STD when the program calls for it – are built into the path, not bolted on at the end.
TYPICAL PATH
Process More.
Send us the RF build
that won't close its loss budget.
Request a capability brief for design rules, attach and interconnect detail, and build data under NDA – GaN, GaAs, AiP, and hermetic RF, assembled on US soil.
/ US-soil / traceable / MIL-STD
RF & mmWave FAQ
Engineer questions.
Do you assemble GaN and GaAs die for RF power?
Yes. We attach GaN and GaAs die for power amplifiers, LNAs, and switches, with the substrate and attach material chosen for the thermal and loss budget of the band you are working in.
Why fluxless, maskless assembly for RF?
Flux leaves residue, and residue is dielectric loss and a reliability risk on a high-frequency interface. Fluxless, maskless assembly keeps the interface clean, so insertion loss stays where you designed it.
Can you build antenna-in-package and mmWave modules?
Yes. We integrate antenna-in-package and mmWave front-end modules, combining flip-chip or wire-bond interconnect, low-loss substrates such as AlN, and hermetic packaging where the application requires it.
Do you package GaN-on-SiC die?
Yes. We attach and package GaN-on-SiC die on US soil for prototype and low-to-mid-volume programs, from commercial RF and power through to aerospace and defense builds. Build data is shared under NDA.
AuSn eutectic or sintered silver for GaN-on-SiC?
Both, chosen by the thermal budget. AuSn when the assembly needs a hermetic, step-soldered build that survives later reflow steps. Sintered silver when power density or die area makes AuSn voiding the limiting risk — it processes cooler and then stays solid far above any later process step.
Why does my GaN die-attach void?
Most often gold dissolution. Thick backside die gold enters the AuSn during reflow and shifts the joint off eutectic, producing skewed melting and voids. An off-eutectic preform sized to absorb the die gold brings the joint back on composition.
What carrier should a GaN-on-SiC power die sit on?
One with a matched CTE. AlN at 4.4 ppm/°C against the die's 3.7 keeps die-attach shear strain near 2.3%. Alumina jumps to 14%, and bare copper reaches about 45%, which cracks die.
What do I get in a capability brief?
Relevant design rules, attach and interconnect detail, applicable materials, and build data for work like yours – shared under NDA. Send the build that has to close its loss budget and we will scope it engineer to engineer.