Advanced Packaging / Die Attach
Die placed to two and a
half microns.
Die attach and die bonding at ±2.5µm @3σ — epoxy, eutectic, sinter and fluxless, die-to-wafer through die-to-PCB, on US soil with placement data captured per unit.
/ ±2.5µm @3σ / Wafer 2″–12″ / ITAR-aware / US-soil
BESI Datacon & Tresky — per-build placement data
Panel-level die attach, no post-attach clean
Wafer sizes handled, including thin die
Attach methods · matched to your stack
Full process detail, design rules, and build data available under NDA.
What we do
The attach step, done four ways.
Die attach decides thermal path, electrical contact, and how the package survives reliability. We pick the method against your requirements — not a house default.
Epoxy
Conductive & non-conductive
Fast, forgiving die attach for general assembly, sensors, and prototypes — cured and characterized for void control.
Eutectic
Au-based, void-controlled
For high-thermal-path and hermetic builds where a metallurgical bond and low void fraction matter.
Sinter
Silver, high-temp
Pressure or pressureless silver sinter for power and high-temperature operation that outlasts solder.
Fluxless
Maskless, clean
No-clean attach for sensitive die and RF surfaces — proven fluxless, maskless on AlN at 100% yield.
Configurations
- 01Die-to-wafer — reconstituted and known-good-die builds
- 02Die-to-die — stacked and side-by-side
- 03Die-to-substrate — ceramic, AlN, organic interposer
- 04Die-to-PCB — chip-on-board into the final assembly
Die & substrate range
- 05Wafer 2″ through 12″, including thin and fragile die
- 06Si (CMOS-compatible), sapphire, AlN, ceramic carriers
- 07Small-pitch, multi-die, and mixed-die-size layouts
- 08Hermetic-ready and reliability-screened builds
Accuracy & tooling
Accuracy you can audit.
±2.5µm @3σ is a measured number, not a brochure claim. Every placement is captured, so the data backs the spec before your unit ships.
BESI Datacon — high-accuracy automated die bonding
Tresky — flexible manual / semi-auto attach & R&D
Placement-data capture — per-unit X/Y/θ logged for SPC
Vision-aligned placement with fiducial and edge referencing for tight, repeatable position.
Bond-line, force and temperature profiles tuned per attach method and die size.
Placement data captured per unit and fed straight into SPC and yield tracking.
Post-attach inspection — X-ray for voids, AOI and metrology — closes the loop.
Anyone can place a die.
Developing the attach is the work.
A new die attach — new die, new substrate, new thermal budget — rarely works on the first recipe. We get it to a stable, documented process window before it costs you a build.
We run attach development as a DOE-driven, SPC-controlled engineering loop: define objectives, build a test vehicle, run the experiment, validate with real metrology, and document the window. See how we develop process with data and AI across every build.
Stacked die & 3D
From one die to a stack.
Tight placement is what makes stacked-die and 3D builds manufacturable. Hold ±2.5µm at the attach step and the interconnect step above it has room to work.
Die attach is the foundation under multi-die modules, interposer stacks, and 3D heterogeneous integration. It pairs with 3D heterogeneous integration and flip chip as part of one advanced packaging flow under a single engineering team.
Where it fits
Built for hard hardware.
Aerospace & Defense
MIL-STD-qualified attach, hermetic-ready, ITAR-aware, US-soil.
Medical & Bio
Small, reliable die attach for implantable-class and sensor builds.
RF & mmWave
Fluxless, low-parasitic attach on AlN and ceramic for RF surfaces.
Advanced Sensors
Thin, fragile, and MEMS die placed at panel scale, 100% yield.
Die attach, answered.
What die placement accuracy can you hold?
We place die to ±2.5µm @3σ on BESI Datacon and Tresky bonders, with placement data captured per unit so the accuracy is proven, not asserted.
Which attach methods do you support?
Epoxy, eutectic, silver sinter, and fluxless. We select the method against your thermal, electrical, reliability and downstream-process requirements rather than defaulting to one recipe.
What configurations and wafer sizes do you handle?
Die-to-wafer, die-to-die, die-to-substrate, and die-to-PCB. Wafer sizes from 2″ to 12″, including thin and fragile die and stacked-die builds for 3D heterogeneous integration.
Can you develop a new die attach process, not just run one?
Yes. We run attach development as a DOE-driven, SPC-controlled loop — objectives, test vehicle, experiment, metrology validation, documented window — before scale-up.
Is the work done in the United States?
Yes. All die attach is performed on US soil, ITAR-aware, with MIL-STD qualification available when the program requires it.
Process More.
Send us the die that
has to land right.
One engineering team, design review through volume. Request a capability brief for attach-method selection, design rules, and build data under NDA.
/ ±2.5µm @3σ / US-soil / ITAR-aware