Advanced Packaging / Flip Chip
Flip chip, fully characterized.
C4 solder, C2 copper-pillar, and Au-stud interconnect with capillary or no-flow underfill — wafer-level, panel-level, and die-direct. One engineering team owns the part from design-rule review through qualified volume, on US soil.
/ ±2.5µm @3σ placement / SPC-controlled / MIL-STD when required / ITAR-aware
Proof, from real flip-chip builds
Bumps in a single C4 package · 100µm pitch · SAC305 · 100% production yield
C4, C2, and Au-stud bump options
100-micron bump pitch, proven in production
Full process detail and design rules available under NDA.
Bump & interconnect
Pick by pitch. All in-house.
Three bump types, two underfill flows, and four die-attach targets — the full flip-chip menu runs under one roof, so the right interconnect gets chosen at design review, not forced by what a vendor can do.
Above ~100 I/O the question stops being interesting: flip chip is the path. Below it, we still flip-chip when parasitic inductance, thermal dissipation, or footprint drive the call.
- 01C4 solder bump — SAC305 mass-reflow workhorse for >130µm pitch. Self-aligning under reflow; underfill on laminate.
- 02C2 copper pillar — fine-pitch wafer-level interconnect below ~130µm, one reflow handles flip-chip and SMD together.
- 03Au-stud bump — thermocompression-bonded to diced die. No wafer-level bumping required — the move for known-good-die, low-volume, and R&D test vehicles.
- 04Capillary underfill — dispensed after reflow, drawn under the die, then cured. Most predictable fill; our production default.
- 05No-flow underfill — applied before placement and cured through reflow to compress the process flow where it fits the design.
- 06Die-to-wafer / die / substrate / PCB — flip-chip attach across all four targets, wafer-level and panel-level.
Substrate by routing density — laminate (BT, FR-4 hi-Tg, polyimide) · co-fired ceramic for hi-rel · thin film when escape routing dictates <50µm trace pitch.
Placement is a data problem.
Flip chip lives or dies on placement accuracy and solder-flow control. We hold ±2.5µm at 3σ on BESI Datacon and Tresky die-attach platforms, with the process under SPC from the first prototype unit.
Mass reflow, thermocompression, and hybrid attach all run here. Fluxless options keep flux residue and post-attach cleaning out of hermetic and RF parts. Every joint is verified — the same x-ray, cross-section, die-shear, and ball-shear that sit on the production line also sit on the prototype line.
Place
±2.5µm @3σ
BESI Datacon & Tresky, SPC-monitored from unit one.
Attach
Reflow / TC / hybrid
Mass reflow, thermocompression, and hybrid attach — fluxless when the part demands it.
Verify
X-ray & cross-section
Void analysis, die shear, ball shear — prototype line runs the same checks as volume.
Case studies
Outcomes, not adjectives.
Three builds from the Heisler line. Names withheld; numbers are real and measured.
02 · Aviation interposer
Fluxless SAC305, capillary & no-flow underfill
High-frequency aviation interposers, 50 per panel, 80µm SAC305 bumps, 60+ joints each — panel-level at 100% yield for an A&D program.
- Bump dia.80µm
- FormatPanel-level
- Yield100%
03 · Fluxless on AlN
Capillary & no-flow underfill, fluxless SAC305
Maskless AlN substrate, 4× CMOS flip chip at 118 I/O each (472 joints/board). Fluxless single-pass reflow under SPC kept molten alloy in place with no solder mask — 100% post-reflow.
- SubstrateAlN
- I/O / die118
- Yield100%
Build data, x-ray imagery, and design rules available under NDA.
Inspection & metrology
If we can't measure it, we don't ship it.
Every flip-chip joint is characterized. X-ray void analysis on Creative Electron, cross-section and failure analysis on Keyence, die shear, and ball shear — the data that proves the joint and feeds the next process iteration.
Voids, bridging, head-in-pillow, and underfill coverage all get caught before they become a field return. See the data engine behind every build on our inspection & metrology page.
Built for the hard ones.
Aerospace & Defense
Qualified, US-soil, ITAR-aware
Co-fired ceramic, hermetic, MIL-STD qualification when required. Panel-level interposers and high-reliability flip chip on domestic capacity. See aerospace & defense packaging.
RF / mmWave
Short paths, low parasitics
Flip chip on AlN and thin-film substrates, fluxless reflow, sub-50µm escape routing where the design demands it. See RF & mmWave packaging.
Flip chip is the floor for 2.5D and 3D. Every interposer stack reduces to flip-chip-style bumping at the die-to-interposer interface — explore advanced packaging and 3D heterogeneous integration.
Flip-chip FAQ
Questions engineers actually ask.
Do you flip-chip diced die without wafer-level bumping?
Yes. Au-stud bumping from a modified wirebonder lets us bond diced, known-good die directly to the substrate — the standard path for KGD-only programs, low-volume, repair, and university test vehicles where the wafer was never bumped at fab.
C4 or C2 — how do you choose?
By pitch and tolerance. C4 solder ball is the mass-reflow workhorse above ~130µm. Below that, C2 copper pillar gives finer placement and lets one reflow handle flip-chip and SMD together. We settle this at design review, before tape-out.
Capillary or no-flow underfill?
Capillary is our production default — dispensed after reflow and drawn under the die for the most predictable fill. No-flow compresses the flow by applying underfill before placement and curing through reflow; we pick the one that fits the die, substrate, and volume.
What placement accuracy do you hold?
±2.5µm at 3σ on BESI Datacon and Tresky die-attach platforms, SPC-controlled from the first prototype unit through volume.
Can you build on AlN, ceramic, or thin-film substrates?
Yes — laminate, co-fired ceramic, and thin film. We have run fluxless, maskless SAC305 reflow on AlN at 118 I/O per die at 100% post-reflow yield. Substrate is chosen by routing density at design review.
Process More.
Bring us the flip chip
that has to work.
One team, design-rule review through qualified volume. Request a capability brief for flip-chip design rules, full process detail, and build data under NDA.
/ US-soil / ITAR-aware / MIL-STD