Capability / Materials
Materials we
already process.
Silicon, sapphire, quartz, AlN, polyimide, underfills, and thin-film metal stacks – characterized on real builds, not a datasheet. If your substrate is on this page, we have run a process on it.
/ Wafer 2in–12in / CMOS-compatible / US-soil
The material set
Substrates and stacks on the floor.
Each material below carries known process windows for dicing, deposition, attach, and inspection. Bring a new one and we will characterize it the same way – test vehicle, DOE, metrology.
Silicon, CMOS-compatible
Device and interposer-grade wafers, 2in through 12in. Thinned die handling, TSV-ready, and back-end-of-line clean – the workhorse for logic, MEMS, and sensor builds.
Sapphire
Hard, optically clear, and thermally stable. UV-laser diced and singulated for photonics, optical windows, and high-reliability sensor packages where a brittle substrate has to come out clean.
Quartz / fused silica
Low-loss, low-CTE substrates for RF, timing, and optical work. Machined and metallized without chipping the edge that matters.
Aluminum nitride (AlN)
High thermal conductivity ceramic for power and RF carriers. Fluxless, maskless die attach demonstrated on 10+ RF boards at 100% yield – heat out, signal clean.
Polyimide & flex
Flexible dielectric for redistribution, flex circuits, and conformal sensor builds. Patterned and laser-processed where rigid substrates will not bend.
Underfills
Capillary and no-flow underfills qualified alongside flip-chip attach to manage thermomechanical stress across >900-bump packages without voiding.
Thin-film metallization
PVD/CVD/ALD metal stacks for pads, seed, RDL, and bond surfaces. Adhesion and barrier layers tuned to the attach and wire-bond step that follows.
Metals & technical ceramics
Lead frames, carriers, and ceramic substrates laser-cut, marked, and prepped for assembly – the parts that hold everything else together.
Detailed material design rules and process windows available under NDA.
Material → process
Pick the substrate. We will tell you the step.
Material choice drives the process. Here is where each one lands, with a link straight to the capability that runs it.
RF substrate selection
Dk is the spec. Df and z-CTE are what bite you.
These are the industry rules we design to — published material properties, not Heisler capability numbers. Pick the laminate for the loss budget and the thermal path, then let the stackup and the plated through-holes follow.
| Material | Dk (10 GHz, process) | Df (10 GHz) | k (W/m·K) | CTE x/y/z (ppm/°C) | Where it wins |
|---|---|---|---|---|---|
| RO4003C | 3.38 ±0.05 design Dk 3.55 |
0.0027 | 0.71 | 11 / 14 / 46 | The general-purpose RF laminate. Low loss with a copper-matched x/y CTE, and it processes like FR-4 in a standard multilayer press. Use the design Dk of 3.55, not the process Dk, or a 50 Ω line lands high. |
| RO4350B | 3.48 ±0.05 design Dk 3.66 |
0.0037 | 0.69 | 10 / 12 / 32 | The flame-retardant sibling of RO4003C. Slightly lossier, and the lowest z-axis CTE in this table, which is why it survives plated through-hole thermal cycling better than the PTFE grades. |
| RT/duroid 5880 | 2.20 ±0.02 | 0.0009 | 0.20 | 31 / 48 / 237 | Lowest loss here, and the choice when the link budget is the whole argument. The 237 ppm/°C z-CTE is the price — see the through-hole note below. |
| RT/duroid 5870 | 2.33 ±0.02 | 0.0012 | — | 22 / 28 / 173 | A tighter-CTE PTFE alternative to 5880 when the board needs more dimensional stability than the very lowest loss. |
| RT/duroid 6002 | 2.94 ±0.04 | 0.0012 | 0.60 | 16 / 16 / 24 | The PTFE grade built for plated through-holes: an isotropic x/y CTE and a z-CTE of 24, an order of magnitude below 5880. This is the low-loss laminate you pick when the design is via-heavy. |
| 96% alumina | 9 at 1 MHz |
0.0004 at 1 MHz |
26 at 20 °C |
6.4 to 7.9 | Thick-film ceramic. Note the Dk and Df here are quoted at 1 MHz, not 10 GHz — they are not interchangeable with the Rogers column. Thermal conductivity falls with temperature, so rate it at the operating junction, not at 20 °C. |
| Aluminium nitride (AlN) | — | — | 140 to 180 | 4.4 | Not a laminate — a carrier. Roughly five to seven times the thermal conductivity of alumina with a CTE close to a GaN-on-SiC die, which is why RF power carriers keep landing on it. See RF and mmWave packaging. |
Sources: Rogers RO4000 datasheet (2026); Rogers RT/duroid 5870-5880 and 6002 datasheets; CoorsTek ADS-96R thick-film design guide; Palomar Technologies AuSn/AuSi application data.
ENIG costs about 0.5 dB per inch on microstrip and about 1.2 dB per inch on grounded coplanar waveguide; over a two-inch launch that is roughly 2.4 dB you never get back.
Source: IPC, Effects of PCB Fabrication on High-Frequency Performance.
Soldermask is not free either. On the same measured passband, adding mask moved insertion loss from 1.89 dB to 2.08 dB — a finish-and-mask decision made at layout, then paid for at every frequency.
Source: IPC, Effects of PCB Fabrication on High-Frequency Performance.
The through-hole caveat. RT/duroid 5880 expands 237 ppm/°C through the thickness. Every reflow and every thermal cycle pulls the plated barrel along with it, so on PTFE builds the via, not the copper trace, is the reliability limiter. If the design is via-heavy, that is the argument for RO4350B at 32 or RT/duroid 6002 at 24.
Why material fit matters
The substrate decides whether it survives.
A wrong material pairing does not fail on the bench. It fails at thermal cycle, at the RF corner, or two years into the field. We screen for that before the build, not after.
Pick the substrate for the physics, then let the process follow. We match coefficient of expansion, conductivity, and surface chemistry to the attach and metrology steps that come next.
Thermal
CTE mismatch and heat path drive solder fatigue and warpage. AlN and matched underfills move heat out and keep the joint intact through cycling.
RF / mmWave
Dielectric loss and surface roughness cost you at high frequency. Low-loss quartz and clean AlN carriers hold the signal where it counts.
Hermeticity
Sealing surfaces and bond-line integrity decide whether moisture stays out of a hermetic package. Material choice and metallization set the hermetic-test result.
Reliability
Adhesion, barrier layers, and clean edges survive screening and MIL-STD qualification. We validate with inspection and metrology on every build.
Proof, from real material builds
Si, sapphire, quartz, AlN, polyimide
Wafer handling range · CMOS-compatible silicon · thinned die
CMOS-compatible, no cross-contamination
Full material design rules, process windows, and build data available under NDA.
Where these materials ship
Built for the hard environments.
Aerospace and defense, medical and bio, RF and mmWave, advanced sensors – the programs where the substrate has to hold up. We process the material set those buyers actually qualify on.
How we engage
Bring the substrate. We bring the data.
- 01Tell us the material, geometry, and the step you need run
- 02We map it to an existing process window or build a test vehicle
- 03DOE and metrology confirm the window before production-intent
- 04Inspection, cross-section, and test validate every build
- 05Documented handoff – one engineering team, on US soil
No material is a mystery if you measure it.
If we have not run your exact stack, we characterize it the same way we characterize everything – with a test vehicle and real metrology, not a guess. Deeper specs are available under NDA.
Process More.
Tell us your substrate.
We will tell you the process.
Request a capability brief for material design rules, process windows, and build data under NDA. One engineering team, design review through volume.
/ US-soil / traceable / MIL-STD