Skip to Content

Resources

Briefs, on request.

Design rules, process windows, and real build data — written engineer-to-engineer. Tell us your application and we send the brief that maps to it. Depth in exchange for a conversation.

Request a capability brief Talk to sales

/ NDA-grade detail / US-soil / MIL-STD when required / ITAR-aware

Multi-chip flip-chip module — representative Heisler advanced-packaging build

Available briefs

Pick the one that matches your build.

Each brief is scoped to a capability. Request it and a process engineer returns the relevant design rules, process windows, and case data under NDA.

Multi-chip flip chip module
Flip Chip Flip-Chip Capabilities

C4 / C2 / Au-stud bumping, capillary and no-flow underfill, fine-pitch placement, and yield data from real high-bump-count builds.

Request brief →
Stacked die advanced package
Advanced Packaging Advanced Packaging

Die attach, wire bond, hermetic, and 3D heterogeneous integration. Placement to ±2.5µm @3σ on BESI Datacon and Tresky.

Request brief →
Silicon interposer 3D render
Wafer-Level Wafer-Level & Interposers

Direct-write litho, TSV, PVD / CVD / ALD, plasma and wet etch, CMP, RDL — WLP, fan-out, and interposer flows.

Request brief →
Laser-micromachined sample
Laser Laser Micromachining

UV 355nm and IR 1064nm. Micro-vias, dicing, singulation, and marking across Si, sapphire, ceramics, metals, and polymers.

Request brief →
Keyence microscope inspection station
Inspection Inspection & Metrology

X-ray, 3D AOI, SEM, sub-micron metrology, and cross-section — the data engine behind every yield number we quote.

Request brief →
Thin RF die build
Custom Tell Us Your Process

Not on the list? Describe the hard step — the one that isn’t working yet — and we scope a brief and a path to it.

Start the conversation →

Inside a brief

Not a datasheet. A build record.

A capability brief is what an engineer needs to decide whether to hand us the work. It is specific, it is referenced to real builds, and it goes under NDA so we can talk numbers instead of adjectives.

Design rules

Pitch, bump, and pad geometry; substrate and material limits; placement tolerance; what we hold and where the edges are.

Process windows

Validated parameter ranges from DOE and SPC — the stable region, not a single demo point, with the metrology that confirms it.

Case data

Yield, defect modes, and reliability results from comparable builds — so you scope against evidence, not a brochure.

Full design rules, process detail, and build data are shared under NDA.

The numbers the briefs are built on

>900

Bumps in one flip-chip package · 100% yield

4,000+

MEMS assemblies · panel-level · 100% yield

±2.5µm

Placement @3σ · BESI Datacon & Tresky

100%

Yield · 50 aviation interposers · 10+ RF boards on AlN

Build-level detail behind every figure is available under NDA.

FAQ

Answers before you ask.

What materials do you process?

Silicon (CMOS-compatible), sapphire, quartz, AlN, polyimide, thin-film metallization, and underfills. Laser work runs across Si, sapphire, ceramics, metals, and polymers. Wafer sizes 2″ through 12″.

What placement accuracy can you hold?

±2.5µm @3σ on BESI Datacon and Tresky platforms — die to wafer, die, substrate, or PCB. Documented builds include a >900-bump flip-chip package at 100% yield. Tighter rules go under NDA.

Which industries do you serve?

Aerospace & defense, medical & bio, RF/mmWave, and advanced sensors. Programs run SPC-controlled, MIL-STD when required, and ITAR-aware.

Is the work done on US soil?

Yes. Engineering, assembly, inspection, and test are performed in the United States with domestic sourcing — one engineering team from design review through volume.

How do I get a brief?

Use the contact form with your application and target specs. A process engineer scopes it and returns the relevant design rules, process windows, and case data under NDA.

Why request one

Scope faster. Guess less.

A brief turns a vague feasibility question into a referenced answer. You see whether your geometry, materials, and tolerances sit inside our proven window before you commit a tapeout or a build slot.

  • 01Real design rules and tolerances, not marketing ranges
  • 02Process windows validated by DOE, SPC, and metrology
  • 03Case data from comparable, documented builds
  • 04A direct line to the engineer who would run your work

Related pillars: Flip Chip · Advanced Packaging · Wafer-Level · Laser · Inspection & Metrology.

Process More.

Tell us the build.
We’ll send the brief.

One form. A process engineer reads it and returns design rules, process windows, and build data matched to your application — under NDA.

Request a Capability Brief

/ US-soil / ITAR-aware / MIL-STD