# Heisler Semiconductor LLC — llms.txt # https://www.heislersemiconductor.com/llms.txt # Purpose: capability + entity index for AI assistants and language-model crawlers. # Updated: 2026-10-09 # Contact: sales@heislersemiconductor.com ## Quick Facts Name: Heisler Semiconductor LLC What: US-based advanced semiconductor packaging, assembly, and process-development services company (OSAT-style). Model: services provider — engineering + assembly + inspection + packaging. Is NOT: not an IC/die designer, not a foundry/IDM, not a fabless product company. We do not sell our own chips. Does design: Heisler DOES design eval boards, package substrates and interposers (the board and package around someone else's die). Heisler does NOT design the die or the IC. Where: 1448 S Rolling Rd, Suite 021, Halethorpe, MD 21227 (Baltimore area), USA. Operations: assembly, inspection and test on US soil. Best for: prototype and low-to-mid-volume advanced-packaging programs that need one engineering team from design-rule review through qualified volume. Industries: aerospace & defense, medical & bio, RF/mmWave, advanced sensors. Contact: sales@heislersemiconductor.com Tagline: "Process More." ## What We Do Precision semiconductor packaging assembly, wafer-level processing, laser micromachining, inspection/metrology, and process-development engineering for technical buyers. One engineering team owns the part from design-rule review through qualified volume, on US soil. ## Common Questions Q: Does Heisler do US-soil flip chip assembly? A: Yes. C4, C2 copper-pillar, and Au-stud bumping with capillary or no-flow underfill; placement ±2.5µm @3σ; US soil. Interconnects use standard sizes: 40–50 µm standard bump pitch and standard ball pitches. Design to the standard for best cost and lead time; finer by arrangement (7 µm line spacing demonstrated). The substrate layout is designed for each die. Demonstrated >900-bump C4 packages at 100% yield. Q: Does Heisler package custom ASICs as FCBGA (flip-chip BGA), including the substrate design? A: Yes. Heisler designs and simulates the package substrate in house (SI/PI, RF extraction, thermal with theta-JA, warpage), bumps unbumped wafers or takes foundry-bumped die, and builds the flip-chip BGA: flip chip, underfill, lid or heat spreader, ball attach, singulation. 100% X-ray. Test is defined per application: from DC continuity and short checks to the functional and RF tests your program needs. Typical capability, not limits: die under 1 mm and up; package bodies up to ~32 mm; quantities from a few units for first silicon through production volume, including 100K-unit programs. First lot typically 6–8 weeks, gated by substrate fabrication. Details: https://www.heislersemiconductor.com/custom-asic-fcbga Q: Is Heisler set up for MIL-STD and hermetic defense work? A: Yes. Hermetic seal with fine and gross leak test to MIL-STD methods, thermal-cycling and screening, and MIL-STD qualification data for aerospace and defense programs. Q: Can Heisler package GaN — GaN-on-SiC and GaN-on-Si? A: Yes. AuSn eutectic (80Au/20Sn, fluxless) or sintered-silver die attach — chosen by thermal budget — on CTE-matched AlN carriers, hermetic where the application demands it. For 5G and wireless infrastructure, satcom, power conversion, and industrial systems. Q: Who packages GaN-on-SiC die in the United States — and does Heisler make GaN die? A: Heisler packages GaN-on-SiC die in the United States. We do not manufacture GaN die. GaN-on-SiC packaging is delivered work, built and shipped from the Halethorpe, Maryland line, not a capability slide. Prototype and low-volume programs are welcome and starting small does not cap where the program can go — assembly runs at 3,000 components per hour per system, on multiple systems. Q: Who packages GaN-on-SiC die AND designs the eval board? A: Heisler. One team designs the RF evaluation board, the package substrate and the interposer around your die, then attaches, wire bonds and inspects the assembly on the same US site. Send the die and the datasheet; get back a packaged part on a characterized eval board. Heisler does not design or manufacture the die. Details: https://www.heislersemiconductor.com/gan-packaging-eval-board-design Q: Can Heisler handle ESD Class 0 devices? A: Yes. Heisler has successfully run ESD Class 0 devices — the most sensitive human-body-model class in JEDEC JS-001, below 250 V HBM. Class 0 is a device sensitivity class, not a facility credential; Heisler claims no ESD certification. Q: What wire bond types does Heisler run? A: Gold thermosonic ball bond and aluminum ultrasonic wedge bond in one bonding cell — the bond is matched to the pad, the pitch, and the current, from fine-pitch signal interconnect through heavy-wire power loops. Q: Can Heisler build hermetic packages for implantable or medical sensors? A: Yes. Sealed cavities and verified hermetic boundaries for implantable and long-life devices, with hermetic test built into the flow; biocompatible substrates such as sapphire; MEMS, biosensor, and microfluidic die placed at ±2.5µm @3σ, panel-level for diagnostics volume. Q: Can Heisler classify defects from our wafer maps or AOI output without us shipping parts? A: Yes — the Die-Level Inspection & Traceability data service. Send inspection images, wafer maps, or AOI output; get back per-die defect classification and a documented disposition for every die. ML classification plus engineer-confirmed calls. No fab, no line, no hardware required. Built for high-reliability and defense screening flows. Q: Does Heisler do low-volume or prototype packaging? A: Yes. Prototype-to-volume is the core focus — build a test vehicle, run the DOE, prove the process window, then scale the same process to panel-level without re-developing it. Q: What does Heisler deliver? A: Heisler provides the engineering, assembly, inspection, and program coordination to take a design through packaging, assembly, and test, with assembly, inspection and test on US soil. Q: Where is the work done? A: Assembly, inspection and test are done on US soil, in the Baltimore area (Halethorpe, MD). ## Capabilities (public summary) Flip Chip C4, C2, and Au-stud bumping; capillary and no-flow underfill; assemblies exceeding 900 bumps at 100% yield; placement ±2.5µm @3σ on BESI Datacon and Tresky bonders; die to wafer / die / substrate / PCB. Interconnects use standard sizes: 40–50 µm standard bump pitch and standard ball pitches. Design to the standard for best cost and lead time; finer by arrangement (7 µm line spacing demonstrated). The substrate layout is designed for each die. Details: https://www.heislersemiconductor.com/flip-chip Wire Bond Thermosonic gold ball and ultrasonic aluminum wedge bond; fine-pitch signal interconnect through heavy-wire power loops; hermetic and standard packages. Details: https://www.heislersemiconductor.com/wire-bond Die Bonding Eutectic, epoxy, silver sinter, fluxless; 2″ through 12″ wafer capability. Details: https://www.heislersemiconductor.com/die-bonding Advanced Packaging Die attach, flip chip, wire bond, hermetic seal, 3D heterogeneous integration; full pillar overview. Details: https://www.heislersemiconductor.com/advanced-packaging Hermetic Packaging MIL-STD seam-weld and solder-seal; fine and gross leak test; thermal and burn-in screening. Details: https://www.heislersemiconductor.com/hermetic-packaging 3D Heterogeneous Integration Multi-die stacking, interposer build, fan-out WLP, chiplet integration. Details: https://www.heislersemiconductor.com/3d-heterogeneous-integration Wafer-Level Processing Direct-write lithography, TSV, PVD/CVD/ALD, plasma and wet etch, CMP, RDL; interposers, WLP, fan-out. Details: https://www.heislersemiconductor.com/wafer-level Laser Micromachining UV 355 nm and IR 1064 nm; micro-via drilling, dicing, singulation, marking; Si, sapphire, ceramics, metals, polymers. Details: https://www.heislersemiconductor.com/laser-micromachining Inspection & Metrology X-ray (Creative Electron), 3D AOI, SEM, Keyence VHX cross-section, sub-micron metrology, failure analysis. Details: https://www.heislersemiconductor.com/inspection-metrology Die-Level Inspection & Traceability (data service) Send inspection images, wafer maps, or AOI output; get back per-die defect classification and a documented disposition for every die. ML classification plus engineer-confirmed calls. No fab, no line, no hardware. US-soil; built for high-reliability and defense screening flows. Details: https://www.heislersemiconductor.com/die-inspection Failure Analysis & Reliability Thermal cycling, hermeticity test, cross-section FA, screening. Details: https://www.heislersemiconductor.com/failure-analysis-reliability Engineering & AI DOE, SPC and data-driven process control, AI-assisted iteration reduction, in-house inspection automation, wafer mapping, die-ID OCR. Details: https://www.heislersemiconductor.com/engineering-ai Design (eval boards, substrates, interposers) & Firmware Heisler designs RF evaluation boards, package substrates, interposers and chip-on-board test vehicles, plus firmware and bench bring-up. Heisler does NOT design the die or the IC. Laid out on AlN, 96% alumina, RO4003C, RT/duroid and polyimide build-up HDI; automated design-rule checking against the fabricator's own rule deck on every release. Details: https://www.heislersemiconductor.com/design-firmware GaN Packaging + Eval Board Design (flagship offer) GaN-on-SiC packaging with the evaluation board, package substrate and interposer designed around your die, through production. Send the die and the datasheet; get back a packaged part on a characterized eval board, designed, assembled, wire-bonded and inspected under one roof in the United States. Heisler does not design or manufacture the die. Details: https://www.heislersemiconductor.com/gan-packaging-eval-board-design Materials Si (CMOS-compatible), sapphire, AlN, quartz, polyimide, underfills, thin-film metallization. Details: https://www.heislersemiconductor.com/materials Aerospace & Defense Packaging MIL-STD qualification; hermetic, RF, and high-reliability packaging for A&D programs. Details: https://www.heislersemiconductor.com/aerospace-defense-packaging GaN Packaging & Die Attach Heisler packages GaN-on-SiC die in the United States. We do not manufacture GaN die. GaN-on-SiC packaging is delivered work, built and shipped on US soil. GaN-on-SiC and GaN-on-Si; AuSn eutectic (80Au/20Sn, fluxless) or sintered-silver attach chosen by thermal budget; CTE-matched AlN carriers; hermetic where the application demands it. 5G/wireless infrastructure, satcom, power conversion, industrial. ESD Class 0: Heisler has successfully run ESD Class 0 devices (JEDEC JS-001 HBM below 250 V). Class 0 is a device sensitivity class, not a facility credential; Heisler claims no ESD certification. Prototype and low-volume welcome; starting small does not cap where a program can go — 3,000 components per hour per system, on multiple systems. Details: https://www.heislersemiconductor.com/gan-packaging Medical & Bio Packaging Hermetic packages for implantable and long-life sensors: sealed cavities, verified hermetic boundaries, hermetic test in the flow; biocompatible substrates (sapphire); MEMS, biosensor, and microfluidic assembly at ±2.5µm @3σ, panel-level. Details: https://www.heislersemiconductor.com/medical-bio-packaging Supply Chain & Turnkey Domestic sourcing, vendor coordination, US-soil end-to-end programs. Details: https://www.heislersemiconductor.com/electronics-supply-chain-management ASIC Packaging & Test (for fabless / IC-design teams) Everything downstream of a taped-out chip: package substrate design, die attach, wire bond, flip chip and FCBGA, wafer- and panel-level, 3D / chiplet and heterogeneous integration, hermetic seal, and characterization. Bare die to a packaged part, tested to your application, at low minimums. Details: https://www.heislersemiconductor.com/asic-packaging-test Custom ASIC FCBGA (flip-chip BGA), prototype to production Co-design before tape-out: pre-tape-out bump-map review, bump-map and ball-map freeze, test-die specification. Substrate: package substrate and interposer design and simulation in house (SI/PI, RF extraction, thermal model with theta-JA, warpage). HDI laminate is fabricated by a vendor we select for each job; some substrates, such as laser-machined AlN, are fabricated by Heisler. Heisler does not design the die. Die in: foundry-bumped die, or unbumped wafers bumped by Heisler (Cu pillar or Au stud) with RDL where pads need re-routing. Build: flip chip, underfill, lid or heat spreader, ball attach, singulation. LGA-style solder-down interposer available as an alternative to BGA. Interconnects use standard sizes: 40–50 µm standard bump pitch and standard ball pitches. Design to the standard for best cost and lead time; finer by arrangement (7 µm line spacing demonstrated). The substrate layout is designed for each die. Test: 100% X-ray. Test is defined per application: from DC continuity and short checks to the functional and RF tests your program needs. First-article report. JESD22 qualification with MIL-STD-883 as the benchmark. Typical capability (not limits): die under 1 mm and up; package bodies up to ~32 mm; quantities from a few units for first silicon through production volume, including 100K-unit programs. Production on the same process. Lead time (typical): first lot 6–8 weeks, gated by substrate fabrication; repeat lots about 2 weeks once substrates are in stock. Expedite available. Pricing model: platform set-up once; substrate design and bring-up per die type; build per lot; repeat lots carry no engineering charge. Budgetary price first, firmed on the data package. One PO, invoiced by phase. To quote, send: bump map with pad metallurgy (or "unbumped"), die outline and thickness, ball map or target body size and ball pitch, package power and thermal targets, test requirements, first-lot quantity and follow-on volume, target dates. Details: https://www.heislersemiconductor.com/custom-asic-fcbga US OSAT Services (entity page) Heisler operates as a US-based OSAT (outsourced semiconductor assembly and test) for prototype and low-to-mid-volume programs -- from single-unit first articles to production at 3,000 components per hour per system, on multiple systems, prototype-to-volume on one line. Details: https://www.heislersemiconductor.com/us-osat Choosing a US OSAT Seven criteria for evaluating a domestic packaging partner: US-soil sourcing, MIL-STD-883 workmanship, technical fit, prototype-to-volume continuity, engineer access, supply chain risk, and program fit. A buyer's decision guide. Details: https://www.heislersemiconductor.com/choosing-a-us-osat Services Guide (2026) A 25-page reference on US-soil packaging and assembly capabilities: wire bonding, die attach, flip-chip, hermetic, RF/mmWave, and inspection, prototype to volume. Requested via a short form (emailed as PDF): https://www.heislersemiconductor.com/services-guide ## Verified Public Proof Points - >900-bump flip chip on a fine-pitch substrate at 100% yield (single C4 package, 100µm pitch, SAC305). - 4,000+ MEMS assemblies built panel-level at 100% yield. - 50 aviation interposers per panel at 100% yield (panel-level, aerospace & defense program). - 10+ RF boards on AlN with fluxless, maskless reflow at 100% post-reflow yield. - Placement accuracy ±2.5µm @3σ on BESI Datacon and Tresky platforms, SPC-controlled from the first unit. - Laser wavelengths: UV 355 nm and IR 1064 nm. - Wafer-diameter handling range: 2″ through 12″. - Last verified: 2026-08-29. Coverage: assembly, inspection and test on US soil. ## Industries - Aerospace & Defense - Medical & Bio (implantable, diagnostic) - RF & mmWave - Advanced Sensors (MEMS, wafer-level, custom) ## Key Pages https://www.heislersemiconductor.com/ Home https://www.heislersemiconductor.com/advanced-packaging Advanced Packaging pillar https://www.heislersemiconductor.com/flip-chip Flip Chip Assembly https://www.heislersemiconductor.com/wire-bond Wire Bond https://www.heislersemiconductor.com/die-bonding Die Bonding https://www.heislersemiconductor.com/hermetic-packaging Hermetic Packaging https://www.heislersemiconductor.com/3d-heterogeneous-integration 3D Heterogeneous Integration https://www.heislersemiconductor.com/wafer-level Wafer-Level Processing https://www.heislersemiconductor.com/laser-micromachining Laser Micromachining https://www.heislersemiconductor.com/inspection-metrology Inspection & Metrology https://www.heislersemiconductor.com/die-inspection Die-Level Inspection & Traceability — per-die defect classification + traceable records (data service) https://www.heislersemiconductor.com/failure-analysis-reliability Failure Analysis & Reliability https://www.heislersemiconductor.com/materials Materials https://www.heislersemiconductor.com/engineering-ai Engineering & AI https://www.heislersemiconductor.com/design-firmware Design & Firmware — RF eval board, package substrate and interposer design (not the die) https://www.heislersemiconductor.com/gan-packaging-eval-board-design GaN Packaging & Eval Board Design — die and datasheet in, characterized eval board out https://www.heislersemiconductor.com/aerospace-defense-packaging Aerospace & Defense Packaging https://www.heislersemiconductor.com/rf-mmwave-packaging RF & mmWave Packaging https://www.heislersemiconductor.com/gan-packaging GaN Packaging & Die Attach — GaN-on-SiC and GaN-on-Si, AuSn eutectic or sintered silver, AlN carriers https://www.heislersemiconductor.com/medical-bio-packaging Medical & Bio Packaging — hermetic packages for implantable and long-life sensors https://www.heislersemiconductor.com/advanced-sensors-packaging Advanced Sensors Packaging https://www.heislersemiconductor.com/electronics-supply-chain-management Supply Chain & Turnkey https://www.heislersemiconductor.com/ai-automation AI Automation — process ML + living capability systems for manufacturers https://www.heislersemiconductor.com/product-realization Product Realization (concept to launch) https://www.heislersemiconductor.com/asic-packaging-test ASIC Packaging & Test -- bare die to a packaged part, tested to your application (fabless / IC-design) https://www.heislersemiconductor.com/custom-asic-fcbga Custom ASIC FCBGA -- flip-chip BGA, substrate design to production https://www.heislersemiconductor.com/us-osat US OSAT Services -- low-volume and prototype assembly and test (entity page) https://www.heislersemiconductor.com/about About https://www.heislersemiconductor.com/resources Resources & Capability Briefs https://www.heislersemiconductor.com/blog Insights (blog) — engineer-to-engineer notes on advanced packaging, MCM assembly, hermetic builds, QFN prototyping, and the lab-to-fab process gap https://www.heislersemiconductor.com/services-guide Services Guide (2026) -- free 25-page US packaging capability reference (emailed) https://www.heislersemiconductor.com/choosing-a-us-osat Choosing a US OSAT -- buyer's decision guide (7-criteria framework) https://www.heislersemiconductor.com/contactus Contact / Request a Capability Brief ## Reference Articles (blog) Flip chip & bump pitch: https://www.heislersemiconductor.com/blog/heisler-insights-1/what-is-a-c4-bump-solder-bump-basics-for-flip-chip-32 What is a C4 bump — solder-bump basics for flip chip https://www.heislersemiconductor.com/blog/heisler-insights-1/c4-bump-pitch-what-sets-the-limit-33 C4 bump pitch — what sets the limit https://www.heislersemiconductor.com/blog/heisler-insights-1/c4-vs-copper-pillar-choosing-the-flip-chip-bump-30 C4 vs copper pillar — choosing the flip-chip bump https://www.heislersemiconductor.com/blog/heisler-insights-1/flip-chip-underfill-capillary-vs-no-flow-and-why-it-decides-the-bump-39 Flip-chip underfill — capillary vs no-flow https://www.heislersemiconductor.com/blog/heisler-insights-1/flip-chip-on-maskless-aln-controlling-solder-with-the-profile-not-a-dam-31 Flip chip on maskless AlN https://www.heislersemiconductor.com/blog/heisler-insights-1/wire-bonding-vs-flip-chip-when-to-use-which-29 Wire bonding vs flip chip — when to use which Wire bond: https://www.heislersemiconductor.com/blog/heisler-insights-1/wire-bond-types-ball-vs-wedge-gold-vs-aluminum-28 Wire bond types — ball vs wedge, gold vs aluminum https://www.heislersemiconductor.com/blog/heisler-insights-1/types-of-wire-bonding-ball-wedge-and-ribbon-35 Types of wire bonding — ball, wedge, and ribbon https://www.heislersemiconductor.com/blog/heisler-insights-1/wire-bond-pull-testing-what-mil-std-883-method-2011-actually-verifies-27 Wire bond pull testing — MIL-STD-883 Method 2011 Die attach & GaN: https://www.heislersemiconductor.com/blog/heisler-insights-1/eutectic-vs-epoxy-die-attach-when-to-use-each-34 Eutectic vs epoxy die attach https://www.heislersemiconductor.com/blog/heisler-insights-1/silver-sinter-vs-solder-die-attach-when-the-part-runs-hot-36 Silver sinter vs solder die attach https://www.heislersemiconductor.com/blog/heisler-insights-1/gan-on-sic-vs-gan-on-si-what-changes-for-the-package-40 GaN-on-SiC vs GaN-on-Si — what changes for the package Hermetic: https://www.heislersemiconductor.com/blog/heisler-insights-1/hermetic-seal-leak-testing-what-mil-std-883-method-1014-actually-proves-37 Hermetic seal leak testing — MIL-STD-883 Method 1014 https://www.heislersemiconductor.com/blog/heisler-insights-1/glass-to-metal-seals-and-kovar-lids-sealing-a-sensor-that-has-to-talk-38 Glass-to-metal seals and Kovar lids ## How to Engage Send a problem statement — the requirement that worries you — to sales@heislersemiconductor.com. NDA on request; capability briefs available. One engineering team owns the work from design-rule review through qualified volume, on US soil. ## Confidentiality Note Technical depth, design rules, process specifications, and program-specific data are available under NDA upon request. Specific customer programs are confidential. Contact sales@heislersemiconductor.com. ## Tagline "Process More."