For fifty years, more performance meant a smaller transistor. Node scaling still moves — but the cost per transistor stopped falling the way it used to, and the gain per node keeps narrowing. The performance the market actually wants now comes increasingly from how chips are packaged together, not from the chips alone.
This is not a fringe argument. Chiplets, 2.5D integration, 3D stacking, heterogeneous die in a single package — these are shipping products from the companies building the highest-performance compute, memory, and RF hardware available. The architectural decision that used to happen at the lithography node now happens at the interconnect: how many die, in what configuration, through what substrate, with what thermal path out. The lever moved from lithography to packaging.
Why the supply chain hasn’t kept up
The CHIPS Act committed roughly $52 billion to domestic semiconductor manufacturing. The National Advanced Packaging Manufacturing Program — the explicit carve-out for advanced packaging — received approximately $3 billion of that. The rest funded front-end wafer fabrication. The funding ratio reflects how the industry thought about packaging for decades: important but downstream, a cost center rather than a performance driver.
That framing is now wrong, and the supply chain is catching up slowly.
- Leading-edge packaging capacity concentrated offshore. The same geography that dominates wafer fabrication — Taiwan, South Korea, Malaysia — also dominates advanced assembly and test. Chiplet integration, 2.5D substrates, and high-density interconnect are built there at scale.
- Domestic tape-out, foreign package. A design team can complete an advanced chip entirely in the United States and still have to leave the country to package it. That is not a domestic supply chain.
- Talent pipeline weighted toward front end. University programs, industry certifications, and career paths train chip designers and process engineers. The back-end knowledge — substrate design, heterogeneous integration, hermetic qualification — built up where the volume work was.
- Packaging lead times, not wafer lead times, set deployment schedules. For defense and aerospace programs, the bottleneck is typically finding a qualified domestic packaging supplier with available capacity and a compliant process — not fab slot availability.
What this means for programs in planning now
If packaging is where performance is won, it is also where the supply chain is most exposed. A program that treats packaging as a commodity back-end step will encounter the bottleneck at the worst possible moment — after tape-out, when the die geometry is fixed and the schedule is already under pressure.
The programs that consistently have more options and shorter timelines are the ones that pull the packaging conversation into architecture, before the die is committed. The package sets real limits on what the die can deliver: the thermal budget, the signal integrity at frequency, the form factor, the qualification path. Those limits need to be in the design loop from the start, not discovered at assembly.
Reshoring the wafer and importing the package is half a strategy. The same applies to treating packaging as the last design decision instead of one of the first.
The domestic advanced-packaging supply base is small. There are a handful of U.S. shops doing wire bonding, die attach, hermetic seal, and multi-chip module assembly at prototype and low-volume production scale. That number needs to grow to match the role packaging now plays in system performance — and in the meantime, programs that engage domestic suppliers early have a measurable advantage over those that don’t.