GaN packaging. The die is the easy part.
GaN and GaAs die attach, interconnect and qualification on US soil — for 5G and wireless infrastructure, satcom, power conversion and industrial systems. GaN-on-SiC and GaN-on-Si, AuSn eutectic and sintered silver attach, AlN carriers, hermetic where the application needs it.
US-soil / prototype & low volume / MIL-STD qualification / build data under NDA
Everyone makes GaN. Far fewer will package yours.
Search for GaN and you get device makers — companies who fabricate GaN parts and package their own. That is a different business from taking someone else's bare die and building it into a qualified assembly at prototype and low volume.
If you have GaN die and need them attached, interconnected, sealed and qualified, you are looking for an assembly service, and the list is short. We are on it, in Maryland, on US soil.
Your substrate decides our package.
The epi is GaN either way. What the package has to cope with is the substrate underneath it — and that choice is made before the die ever reaches us.
Heat leaves through the die
Silicon carbide carries roughly 3.3 W/(cm·K) at room temperature, so the die moves heat into the attach layer efficiently — and the attach becomes the next bottleneck rather than the substrate. It expands at about 3.7 ppm/°C, which sets the carrier choice. This is the usual substrate for RF power and the one most of our GaN work sits on.
Heat becomes the package's problem
Cheaper, on larger wafers, and increasingly common in power conversion. Silicon carries less heat than SiC and adds a less favourable thermal boundary at the GaN interface, so more of the thermal burden shifts onto the attach and the carrier. It also expands differently, so a carrier chosen for a SiC-based die is not automatically right here.
Tell us which one you have. It changes the attach material, the carrier, and what the qualification plan has to prove.
Match the carrier to the substrate, not to the GaN.
This is the most common reason a GaN package passes assembly and then fails thermal cycling. A GaN-on-SiC die expands with its substrate, about 3.7 ppm/°C. The carrier under it has to live with that across every cycle.
Close match. The default carrier under a hard-soldered GaN die, and the reason AlN keeps appearing in RF power assemblies.
Marginal. Workable in some geometries, but the strain grows with die size and the margin disappears quickly.
Cracks die under a hard solder joint. Excellent thermally, and that is exactly the trap.
When a joint still fails, the levers are a softer attach, a thicker bondline, a smaller die, or a better-matched carrier — in that order of cost.
Two routes, chosen by the thermal budget.
80Au/20Sn, fluxless
Re-melts at 280 °C, so it survives a later lid step and board-level reflow without floating the die. The route for hermetic, step-soldered builds.
High-temperature, not reworkable
Processes at 200-250 °C and then stays solid far above that. The route when power density or die area makes voiding the limiting risk.
We run both, and which one a build gets is a calculation rather than a house preference. Full attach detail, including the off-eutectic preform work that thick backside gold requires, is on our RF and mmWave packaging page, and the wider attach families on die bonding.
Built for commercial and industrial GaN.
5G & wireless
Infrastructure amplifiers where efficiency and thermal path decide the enclosure.
Satcom
Terminal and ground-segment amplifier modules, including Ka-band assemblies.
Power conversion
EV, charging and industrial power, where operating temperature drives the attach choice.
Industrial
Continuous-duty systems where the part never gets a chance to cool down.
You get the failure-mode distribution.
- 01X-ray for voids, before and again after cycling
- 02Die shear to MIL-STD-883 Method 2019
- 03Wire-bond pull and ball shear to Methods 2011 and 2023
- 04Thermal cycling to Method 1010, -55 to +125 °C
- 05Hermetic seal and leak test where the application requires it
Build data, void measurements and design rules are available under NDA.
Coupon first. Then scale.
We start with a test vehicle that exercises the hard part of your build — the attach, the interconnect, the thermal path — and prove it against real metrology before anyone commits a full lot.
Engineer questions.
Who packages GaN die in the United States?
We do — GaN and GaAs die attach and packaging in Halethorpe, Maryland, on US soil, at prototype and low volume. It is worth being precise about the distinction: most of the names that come up in a GaN search are device makers who package their own parts. If you have bare GaN die and need someone to attach, interconnect and qualify them, that is an assembly service, and there are far fewer of those.
What is the difference between packaging GaN-on-SiC and GaN-on-Si?
The epi layer is GaN either way; the substrate underneath it is what the package has to deal with. Silicon carbide conducts heat well — roughly 3.3 W/(cm·K) at room temperature — so a GaN-on-SiC die gets heat out through its own substrate and the attach layer becomes the next bottleneck. GaN-on-Si is cheaper on larger wafers, but silicon carries less heat and adds a less favourable thermal boundary at the GaN interface, so more of the thermal burden lands on the package. The two also expand at different rates, which changes the carrier choice.
Why does the carrier material matter so much for GaN?
Because you match the carrier to the die's substrate, not to the GaN epi. A GaN-on-SiC die expands at roughly 3.7 ppm/°C. Aluminium nitride at about 4.4 ppm/°C is close enough to survive hard-soldered attach and thermal cycling; alumina at about 7.9 ppm/°C is marginal; bare copper at about 17 ppm/°C will crack die. That mismatch is the single most common reason a GaN package fails qualification rather than assembly.
Which die attach do you use for GaN?
Two routes, chosen by the thermal and process budget rather than by preference. AuSn eutectic (80Au/20Sn, fluxless) re-melts at 280 °C, so it survives a later lid step and board-level reflow without floating the die — the route for hermetic, step-soldered builds. Sintered silver processes at 200-250 °C and then stays solid far above that, which is the route when power density or die area makes voiding the limiting risk. Sinter is not reworkable.
Can you handle GaN die with thick backside gold?
Yes, and it is worth flagging because it catches people out. Gold from the die backside dissolves into an AuSn joint during reflow, pushing the alloy off eutectic so it melts unevenly and voids — and the process window looks healthy right up until the X-ray. The fix is an off-eutectic preform sized so the gold the die contributes brings the joint back to eutectic as it melts. Tell us the backside metallisation stack early.
What GaN applications do you support?
Commercial and industrial GaN work: 5G and wireless infrastructure amplifiers, satcom terminals, power conversion including EV and charging, and industrial systems. RF and microwave module work is covered in more depth on our RF and mmWave packaging page.
How is a GaN package qualified?
X-ray for voids, die shear to MIL-STD-883 Method 2019, wire-bond pull and ball shear to Methods 2011 and 2023, and thermal cycling to Method 1010 from -55 to +125 °C with a second X-ray after cycling. You get the failure-mode distribution, not just a pass count.
Can you start with a test coupon before a full build?
That is how we prefer to start. A coupon or test vehicle that exercises the hard part — the attach, the interconnect, the thermal path — gets proven against real metrology before anyone commits a full lot. One engineering team carries it from that coupon through qualification.
Send us the GaN die that has to stay cool.
Request a capability brief for GaN attach routes, carrier selection, qualification detail and build data under NDA — assembled on US soil.