Custom ASIC FCBGA
Custom ASIC FCBGA, prototype to production.
FCBGA (flip-chip BGA) packaging for your custom ASIC. We design the package substrate, bump your wafers or take your bumped die, and build the flip-chip BGA. Every unit is X-rayed, and test is defined per application. Prototype lots to production, on the same process.
/ Substrate design in house / 100% X-ray / JESD22 qualification
Typical capability
Sizes, quantities, lead times.
These are typical, not limits. Outside them? Send the data and ask.
Under 1 mm and up
Small die are welcome. The substrate layout is designed for each die.
Up to ~32 mm
Body size set by your ball map, or by a target body we propose.
First silicon to production
From a few units for first silicon through production volume, including 100K-unit programs.
Standard sizes
40–50 µm standard bump pitch and standard ball pitches. Finer by arrangement.
Typically 6–8 weeks
Gated by substrate fabrication.
About 2 weeks
Once substrates are in stock. Expedite available.
01 / Co-design, before tape-out
Freeze the bump map before you tape out.
The cheapest package fix happens before tape-out. We review your bump map against the substrate it has to escape into. Then we freeze the bump and ball maps with you, and write a test-die spec if you want one built first.
- 01Pre-tape-out bump-map review
- 02Bump-map and ball-map freeze
- 03Test-die specification
The flip-chip design rules behind the review: flip chip assembly
02 / Substrate design and simulation
We design the substrate. Then we simulate it.
Package substrate and interposer design are done in house, from your ball map or one we propose. Simulation runs in house too, before anything goes to fab.
- 01SI/PI on the signal and power paths
- 02RF extraction on the fast nets
- 03Thermal model with θJA
- 04Warpage
- 05Lid or heat-spreader choice
We design the package around your die. We do not design the die.
Eval boards, substrates and interposers: design capability
03 / Sourcing
Substrate fab, matched to the stackup.
HDI laminate is fabricated by a vendor we select for each job. We choose it against the stackup and the schedule, and we handle the tooling and prototype panels.
Some substrates we fabricate ourselves, such as laser-machined AlN. Either way, one team owns the design, the vendor and the build.
AlN and other substrates: materials · laser micromachining
04 / Build
Wafer or die in. FCBGA out.
Send foundry-bumped die, or send unbumped wafers and we bump them.
- 01Bumping from unbumped wafers: Cu pillar or Au stud, with RDL where the pads need re-routing
- 02Flip chip
- 03Underfill
- 04Lid or heat spreader
- 05Ball attach
- 06Singulation
Not every part needs balls. We also build an LGA-style solder-down interposer that solders straight onto your board, as an alternative to BGA.
Interconnects use standard sizes: 40–50 µm standard bump pitch and standard ball pitches. Design to the standard for best cost and lead time; finer by arrangement (7 µm line spacing demonstrated). The substrate layout is designed for each die.
Bumping and RDL: wafer-level processing · flip chip assembly
05 / Test and qualification
X-ray on every unit. Test to your application.
Test is defined per application: from DC continuity and short checks to the functional and RF tests your program needs.
- 01100% X-ray
- 02Test plan defined with you, per application
- 03First-article report
- 04JESD22 qualification, with MIL-STD-883 as the benchmark
Inspection and reliability: inspection & metrology · failure analysis & reliability
06 / Prototype to production
Same process, prototype to production.
The process that builds your prototype lot is the one that builds production. Scale the lot size, not the process.
Quantities run from a few units for first silicon through production volume, including 100K-unit programs.
Packaging a taped-out chip another way, such as wire bond, chiplet or hermetic? Start at ASIC packaging & test
How we price it
Set up once. Each new die costs less.
Platform, once
We set up the process for your package family one time.
Per die type
Substrate design and bring-up.
Per lot
The build. Repeat lots carry no engineering charge.
How quoting works
- 01A budgetary price first, from what you can share today
- 02A firm price once the data package is in
- 03Expedite available
- 04One PO, invoiced by phase
To quote it
What to send us.
Send what you have today. We price from it, and firm the price once the rest is in. NDA on request.
Request a capability brief- 01Bump map: locations, pad size, pad metallurgy, bump type (or “unbumped”)
- 02Die outline, thickness and dicing tolerance
- 03Bumped die, or unbumped wafers (give the wafer size)
- 04Ball map or pin-out, or a target body size and ball pitch
- 05Signal and power summary: fastest signal, package power
- 06Thermal targets: Tj max and ambient
- 07Test requirements: from a DC probe sequence with current and voltage limits to the functional and RF tests you need
- 08Quantities and dates: first-lot quantity, follow-on volume, target dates
- 09Qualification target, if you have one
- 10Optional: S-parameter data for nets you want simulated
Proof
From real flip-chip builds.
Names withheld. The numbers are real.
>900 bumps
In one C4 package: 60 µm bumps on 100 µm pitch, 100% production yield.
4,000+ assemblies
MEMS assemblies built panel-level at 100% yield.
50 per panel
Aviation interposers, 50 per panel, at 100% yield.
10+ boards
118 I/O per die, 472 joints per board, 100% post-reflow.
Build detail: flip chip assembly. Full data under NDA.
Questions engineers ask
Custom ASIC FCBGA, answered.
Do you design the FCBGA substrate?
Yes. Package substrate and interposer design are done in house, with SI/PI, RF extraction, thermal (θJA) and warpage simulation. HDI laminate is fabricated by a vendor we select for each job. We design the package around your die, not the die itself.
Can you package unbumped wafers, or only bumped die?
Both. Send foundry-bumped die, or send unbumped wafers and we bump them with Cu pillar or Au stud, adding RDL where the pads need re-routing.
What die sizes, package sizes, pitches and quantities do you build?
Typical capability, not limits: die under 1 mm and up, package bodies up to ~32 mm, and quantities from a few units for first silicon through production volume, including 100K-unit programs. Interconnects use standard sizes: 40–50 µm standard bump pitch and standard ball pitches. Design to the standard for best cost and lead time; finer by arrangement (7 µm line spacing demonstrated). The substrate layout is designed for each die.
How long does the first lot take?
Typically 6–8 weeks, gated by substrate fabrication. Repeat lots run in about 2 weeks once substrates are in stock. Expedite is available.
What testing is included?
Every unit is X-rayed. Test is defined per application: from DC continuity and short checks to the functional and RF tests your program needs. You also get a first-article report, and JESD22 qualification is available, with MIL-STD-883 as the benchmark.
What do I send to get a quote?
Send the bump map and pad metallurgy, the die outline and thickness, a ball map (or a target body size and ball pitch), your test requirements, and the quantity and dates. We send a budgetary price first and firm it once the full data package is in.
Process More.
Send the bump map. Get an FCBGA plan back.
Substrate design, bumping, flip-chip BGA build, X-ray and test to your application, from prototype lot to production. Request a capability brief, or send your data package under NDA.
/ Substrate design / 100% X-ray / NDA on request