Two dies can both be GaN and give you completely different packaging problems. The epi layer is the same material; what differs is the substrate it was grown on, and the substrate is what the package actually has to deal with. That choice is made long before the die reaches an assembly house — but it determines the attach material, the carrier, and how much of the thermal budget lands on the package rather than on the die.
What the substrate is actually doing
Heat generated in the GaN channel has to get out, and its first route is downward through the substrate. So the substrate is not passive packaging material — it is the first element of the thermal path, and its conductivity sets how much work everything below it has to do.
Silicon carbide is good at this. SiC carries roughly 3.3 W/(cm·K) at room temperature, which is why a SiC-based amplifier runs cooler than the same design on a poorer substrate. The practical consequence for us: the die hands heat off efficiently, and the attach layer becomes the bottleneck. Get the attach wrong on GaN-on-SiC and you have wasted the substrate you paid for.
Silicon is the cost-and-scale answer: cheaper, on larger wafers, and increasingly common in power conversion. It carries less heat than SiC, and there is a less favourable thermal boundary where the GaN meets the silicon. Both effects push in the same direction — more of the thermal burden shifts onto the package. We deliberately do not publish figures for that boundary resistance; the ones in circulation vary widely with epi structure and buffer design, and quoting a number we cannot stand behind would be worse than saying the direction plainly.
The carrier is matched to the substrate, not to the GaN
This is the single most useful thing to know about GaN packaging, and it is where designs go wrong. A die expands according to its substrate, because that is where nearly all of its thickness is. A GaN-on-SiC die moves at roughly 3.7 ppm/°C — a SiC number, not a GaN number.
So the carrier has to be matched to that, and the spread between candidates is not subtle:
- Aluminium nitride, about 4.4 ppm/°C — close. This is the default carrier under a hard-soldered GaN die, and the reason AlN is everywhere in RF power assemblies.
- 96% alumina, about 7.9 ppm/°C — marginal. Workable in some geometries, and the margin shrinks as die size grows.
- Bare copper, about 17 ppm/°C — cracks die under a hard solder joint. Copper is thermally excellent, which is precisely what makes it a trap.
A GaN-on-Si die does not expand at the same rate as a GaN-on-SiC one, so a carrier stack chosen for one is not automatically right for the other. Changing substrate mid-programme is not a drop-in substitution at the package level, even though the die looks equivalent on a datasheet.
What changes in the attach
Because GaN-on-SiC pushes the bottleneck into the attach, the attach choice gets scrutiny it would not otherwise get. Two routes cover most work, and the decision is a calculation rather than a preference:
AuSn eutectic, 80Au/20Sn and fluxless, re-melts at 280 °C. That high re-melt is the point: the joint survives a later lid seal and board-level reflow without the die floating. It is the route for hermetic, step-soldered builds.
Sintered silver processes at 200-250 °C and then stays solid far above that, which matters when the part runs hot continuously. It is the route when power density or die area makes voiding the limiting risk, and it is not reworkable.
The failure mode worth knowing before you quote
GaN die often arrive with thick backside gold. That gold dissolves into an AuSn joint during reflow, which pushes the alloy composition off eutectic — so it melts unevenly and voids. The uncomfortable part is that the process window looks perfectly healthy until the X-ray comes back.
The fix is an off-eutectic preform, sized so that the gold the die contributes brings the joint back to eutectic as it melts. It works reliably, but only if the backside metallisation stack is known up front. It is the first thing worth telling an assembly partner about a GaN die, and the thing most often left out of an RFQ.
What changes in qualification
The thermal cycling result is where a substrate-carrier mismatch shows up, not the assembly yield. A package with the wrong carrier can assemble cleanly, X-ray cleanly, and then fail after cycling — which is an expensive place to learn.
So the qualification worth running is X-ray for voids, die shear to MIL-STD-883 Method 2019, wire-bond pull and ball shear to Methods 2011 and 2023, and thermal cycling to Method 1010 from -55 to +125 °C with a second X-ray after cycling. The second X-ray is the one that distinguishes a package that was built correctly from one that merely started that way.
Where to start
Four facts settle a GaN packaging conversation almost entirely:
- Which substrate the die is on — SiC or Si, because it changes everything below it.
- The backside metallisation stack, especially gold thickness.
- Die size, since strain from any carrier mismatch scales with it.
- Worst-case continuous dissipation, and whether the part ever gets to cool.
We attach and qualify GaN and GaAs die in Halethorpe, Maryland, on US soil, for 5G and wireless infrastructure, satcom, power conversion and industrial systems. More on GaN packaging and die attach, the RF module side on RF and mmWave packaging, and the wider attach families on die bonding. If sinter is the route you are weighing, the trade is in silver sinter versus solder.
Answered.
What is the difference between GaN-on-SiC and GaN-on-Si for packaging?
The epi is GaN in both cases; the substrate underneath differs, and the substrate is the first element of the thermal path. Silicon carbide carries heat well — roughly 3.3 W/(cm·K) at room temperature — so the die offloads heat efficiently and the attach layer becomes the bottleneck. Silicon is cheaper on larger wafers but carries less heat and adds a less favourable boundary at the GaN interface, shifting more of the thermal burden onto the package. The two also expand at different rates, which changes the carrier.
Why is the carrier matched to the die substrate instead of the GaN?
Because nearly all of the die's thickness is substrate, so the substrate sets how the die expands. A GaN-on-SiC die moves at roughly 3.7 ppm/°C, which is a SiC figure. Match the carrier to that: aluminium nitride at about 4.4 ppm/°C survives, 96% alumina at about 7.9 ppm/°C is marginal, and bare copper at about 17 ppm/°C will crack die under a hard solder joint despite being thermally excellent.
Can you swap from GaN-on-SiC to GaN-on-Si without changing the package?
Not safely. The two substrates expand at different rates, so a carrier stack chosen for one is not automatically correct for the other, and the attach and thermal design may both shift. The die can look equivalent on a datasheet while the package needs requalifying.
Why does thick backside gold on a GaN die cause problems?
Gold from the die backside dissolves into an AuSn joint during reflow and pushes the alloy off eutectic, so it melts unevenly and voids — and the process window looks healthy right up until the X-ray. The fix is an off-eutectic preform sized so the gold the die contributes carries the joint back to eutectic as it melts. It needs the metallisation stack known up front.
How should a GaN package be qualified?
X-ray for voids, die shear to MIL-STD-883 Method 2019, wire-bond pull and ball shear to Methods 2011 and 2023, and thermal cycling to Method 1010 from -55 to +125 °C with a second X-ray after cycling. A carrier mismatch typically passes assembly and fails after cycling, so the post-cycling X-ray is the measurement that matters.
Who packages GaN die in the US?
We attach, interconnect and qualify GaN and GaAs die in Halethorpe, Maryland, on US soil, at prototype and low volume. Worth noting that most names surfaced by a GaN search are device makers packaging their own parts — if you have bare die and need an assembly service, that is a much shorter list.