OSAT stands for Outsourced Semiconductor Assembly and Test. A fab makes die; an OSAT turns those die into packaged, tested parts you can put on a board. The model exists because assembly and test are capital-heavy and process-heavy, and almost nobody who designs a chip wants to own that equipment. The question is never whether to outsource packaging. It is which kind of shop matches where your program actually is.
The volume math that decides everything
A high-volume OSAT is an efficiency engine. Its economics come from repetition — the setup, tooling and qualification for a package get amortised across tens of thousands of units a year, and below that the setup dominates the bill. This is not a flaw. It is the entire point of the model, and at commodity volume in a settled package it is very hard to beat.
At the opposite end, a university lab or an in-house bench can build a handful of parts. That works right up until someone asks for twenty more that are identical, or for the documentation showing why they are.
Between those two sits the band where most funded programs actually live: hundreds to low thousands of units, with the design still moving. That band is not an underserved market segment. It is missing infrastructure — too small to interest a production line, too demanding for a bench.
What the middle band actually needs
It needs the processes, not a scaled-down production flow. Concretely, that means die attach across the alloy families rather than one house default — AuSn, AuSi, AuGe and AuIn, tin-silver-copper, indium-based systems, high-lead, and silver sinter — chosen against the part's operating temperature and its die backside metallisation, which is what actually constrains the choice.
It means flip chip where the interconnect suits the substrate rather than the other way round. C4 solder bumping runs to a 40–50 µm minimum pitch. Solder-capped copper pillar goes finer than C4, how much finer depending on the program. Gold stud bump sits at about 40 µm. Where the substrate cannot survive a solder reflow at all — glass, polyimide, MEMS — anisotropic conductive adhesive has run here down to 7 µm pitch, cured near 150 °C with no reflow and no underfill cure.
It means handling die that punish handling. We have built GaN-on-SiC packaging, and we have run ESD Class 0 parts — the most sensitive human-body-model class — successfully. Wide-bandgap and high-electron-mobility die are unforgiving in exactly the phase where a program can least afford a lost lot.
And it needs engineering around the process, not just access to it. In development the substrate, the land pattern and the evaluation board are usually still open questions, and a packaging house that can design them with you shortens the loop by a turn. It also needs data: every die we place and every bond we make goes into a structured inspection record, reviewed by the engineer who ran it, so when a lot behaves differently the answer is in the log rather than in someone's memory. See our die-level inspection and traceability and design and engineering pages.
When each answer is the right one
Send it offshore when the part is a settled design in a standard outline at commodity volume. If your part is a QFN in the hundreds of thousands and the process is not changing, a high-volume OSAT will beat us on price, and we will say so. We would rather decline that quote than lose the program where we are actually the right answer.
Build it in-house when packaging is your product — when the process is the differentiator you are raising money against. Budget twelve to eighteen months and real capital before the first good part.
Use a US prototype-scale house when the design is still moving. The cost that sinks development programs is not price per unit, it is iteration latency. Packaging routinely gets four weeks on a tape-out schedule and it is never four weeks — substrate selection, land patterns, test sockets, process flow and inspection criteria all resolve after someone tries to build the thing. Offshore, each of those turns is freight plus a time-zone relay through a program manager. Here, it is days, and you talk to the engineer running the tool. Bring a packaging partner in eight to twelve weeks before tape-out, or accept that the first run is a learning run and budget for it.
We run die attach, wire bond, flip chip and hermetic sealing from bare die in Halethorpe, Maryland, at prototype through low volume. More on the processes on our die bonding, wire bond and flip chip pages.
Answered.
What does OSAT stand for?
OSAT stands for Outsourced Semiconductor Assembly and Test. It is the company that takes finished wafers or bare die and turns them into packaged, tested parts — die attach, wire bond or flip chip, encapsulation or hermetic sealing, and electrical test. A fab makes die; an OSAT makes a part you can put on a board.
When does a US OSAT make sense instead of an offshore one?
When the design is still changing. Offshore assembly is hard to beat at commodity volume in a settled package, and weak on anything that needs process development or fast iteration. A US prototype-scale house wins on iteration latency: each design turn costs days rather than freight plus a time-zone relay, and you speak to the engineer running the process. If your part is high volume in a standard outline and the process is settled, offshore is the correct answer and we will tell you so.
What is the minimum volume for an OSAT?
High-volume assembly economics generally need tens of thousands of units a year to amortise setup, tooling and package qualification. Below that the setup dominates the cost, which is why programs building hundreds to low thousands of units often cannot get quoted at all. That band is the one we serve.
Who does semiconductor packaging in the US at prototype volume?
We do, in Halethorpe, Maryland — die attach, wire bond, flip chip and hermetic sealing from bare die, at prototype through low volume, on US soil. Die attach spans the eutectic, solder, indium and silver-sinter families; flip chip covers C4 solder at 40–50 µm minimum pitch, solder-capped copper pillar finer than that, gold stud at about 40 µm, and anisotropic conductive adhesive demonstrated to 7 µm pitch on substrates that cannot take a reflow.
Can you handle GaN, SiC and ESD-sensitive die?
Yes. We have built GaN-on-SiC packaging, and we have successfully run ESD Class 0 parts — the most sensitive human-body-model class. Wide-bandgap die and high-electron-mobility devices are least forgiving exactly when a program can least afford to lose a lot, which is the phase we work in.